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The SystemVerilog spec describes a scheduler model in Figure 4-1 (p. 67 of IEEE 1800-2023). It describes a number of regions, including an Active region set and a Re-Active region set.

Orthogonally, it also describes a set of dedicated PLI regions, some of which are in the Active set, and some in the Re-Active set.

The spec then goes on to describe PLI callback control points in Table 4-1 of Section 4.10 (p. 72). This table describes 7 PLI backs (which are actually VPI callbacks in Chapter 38), and their mapping to event regions.

The mapped regions, however, are all in the Active region set (and the Pre-Postponed and Postponed regions). There are no callbacks that map to any Re-Active region.

So how does a VPI application schedule things in any Reactive region? Indeed, how is anything scheduled in the Reactive PLI region set? I cannot find any reference elsewhere in the spec.

The SystemVerilog spec describes a scheduler model in Figure 4-1 (p. 67 of IEEE 1800-2023). It describes a number of regions, including an Active region set and a Re-Active region set.

Orthogonally, it also describes a set of dedicated PLI regions, some of which are in the Active set, and some in the Re-Active set.

The spec then goes on to describe PLI callback control points in Table 4-1 of Section 4.10 (p. 72). This table describes 7 PLI backs (which are actually VPI callbacks in Chapter 38), and their mapping to event regions.

The mapped regions, however, are all in the Active region set (and the Pre-Postponed and Postponed regions). There are no callbacks that map to any Re-Active region.

So how does a VPI application schedule things in any Reactive region? Indeed, how is anything scheduled in the Reactive PLI region set? I cannot find any reference elsewhere in the spec.

• verilog
• system-verilog
• vpi

Share Improve this question Follow edited Mar 26 at 2:39 garethw asked Mar 26 at 2:34 garethwgarethw 5366 bronze badges

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Sorted by: Reset to default 2

The LRM is missing this due to lack of volunteers to address this section of VPI specification. They remain as open issues. here is a link to one of them

https://accellera.mantishub.io/view.php?id=1764

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