stm32f1 - why PLL not change in STM32f103c8 - Stack Overflow

admin管理员组

文章数量:1323732

I have written the following code snippet to set the system clock to 32MHz.

#include "stm32f10x.h"

void SystemClock_Config(void);


int main(void)
{
  SystemClock_Config();

  while(1){}

  return 0;
}

void SystemClock_Config(void) 
{
  RCC->CR |= (1<<16);//HSE clock enable >> High Speed External
  while(!(RCC->CR & (1<<17))); //External high-speed clock ready flag
  RCC->CR &= ~(1<<24);//PLL OFF
  RCC->CFGR &= ~(0xf<<18);
  RCC->CFGR |= (0x2<<18); //PLL multiplication facto >> PLL input clock x 4
  RCC->CR |= (1<<24); //PLL enable
  while(!(RCC->CR & (1<<25))); //PLL clock ready flag  
  RCC->CFGR |= (1<<1); // System clock Switch >> PLL selected as system clock
  while(!(RCC->CFGR & (1<<3))); //System clock switch status >> PLL used as system clock
  RCC-> CFGR &= ~(0xf<<4);
  RCC-> CFGR |= (0x8<<4); //AHB prescaler >> SYSCLK divided by 2
  RCC-> CFGR &= ~(0x7<<11);
  RCC-> CFGR |= (0x0<<11); //APB high-speed prescaler (APB2) >> 0xx: HCLK not divided
  RCC-> CFGR &= ~(0x7<<8);
  RCC-> CFGR |= (0x4<<8);//APB Low-speed prescaler (APB1) >> 100: HCLK divided by 2
  RCC-> APB2ENR |= ((1<<2)|(0x1<<0)); //I/O port A clock enable & Alternate function I/O clock enable
  //RCC-> APB2ENR |= ((1<<2)); //I/O port A clock enable
  RCC-> CFGR &= ~(0xf<<24); 
  RCC-> CFGR |= (0x4<<24); //Microcontroller clock output >> System clock (SYSCLK) selected
  
}

But after debugging, as shown in the picture, the PLL value still remains at 9.

Are my settings wrong? Or do I have to meet certain conditions to apply the settings? Please advise. thanks

I have written the following code snippet to set the system clock to 32MHz.

#include "stm32f10x.h"

void SystemClock_Config(void);


int main(void)
{
  SystemClock_Config();

  while(1){}

  return 0;
}

void SystemClock_Config(void) 
{
  RCC->CR |= (1<<16);//HSE clock enable >> High Speed External
  while(!(RCC->CR & (1<<17))); //External high-speed clock ready flag
  RCC->CR &= ~(1<<24);//PLL OFF
  RCC->CFGR &= ~(0xf<<18);
  RCC->CFGR |= (0x2<<18); //PLL multiplication facto >> PLL input clock x 4
  RCC->CR |= (1<<24); //PLL enable
  while(!(RCC->CR & (1<<25))); //PLL clock ready flag  
  RCC->CFGR |= (1<<1); // System clock Switch >> PLL selected as system clock
  while(!(RCC->CFGR & (1<<3))); //System clock switch status >> PLL used as system clock
  RCC-> CFGR &= ~(0xf<<4);
  RCC-> CFGR |= (0x8<<4); //AHB prescaler >> SYSCLK divided by 2
  RCC-> CFGR &= ~(0x7<<11);
  RCC-> CFGR |= (0x0<<11); //APB high-speed prescaler (APB2) >> 0xx: HCLK not divided
  RCC-> CFGR &= ~(0x7<<8);
  RCC-> CFGR |= (0x4<<8);//APB Low-speed prescaler (APB1) >> 100: HCLK divided by 2
  RCC-> APB2ENR |= ((1<<2)|(0x1<<0)); //I/O port A clock enable & Alternate function I/O clock enable
  //RCC-> APB2ENR |= ((1<<2)); //I/O port A clock enable
  RCC-> CFGR &= ~(0xf<<24); 
  RCC-> CFGR |= (0x4<<24); //Microcontroller clock output >> System clock (SYSCLK) selected
  
}

But after debugging, as shown in the picture, the PLL value still remains at 9.

Are my settings wrong? Or do I have to meet certain conditions to apply the settings? Please advise. thanks

• stm32f1

Share Improve this question Follow asked Jan 12 at 6:39 Hossein AmeriHossein Ameri 1122 bronze badges 1

• Where do you see a 9 in there? – Tim Roberts Commented Jan 12 at 6:50

Add a comment  | 

1 Answer 1

Sorted by: Reset to default 0

After many attempts, I realized the problem. The problem is with the following line...

RCC->CFGR |= (1<<1); // System clock Switch >> PLL selected as system clock

This line should be modified as follows

 RCC->CFGR |= 0x1; // System clock Switch >> HSE selected as system clock

本文标签： stm32f1why PLL not change in STM32f103c8Stack Overflow