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I'm trying to describe a generic multi-bit register, with N bit input and output signals, a reset bit and an enable bit for writing to the register, but even though it works properly in the behavioral simulation, it stops functioning when I do a post-synthesis simulation.

My g_register.vhd is as follows:

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;

entity g_register is
    generic (
        N : integer := 8
    );
    port (
        rst      : in std_logic;
        clk      : in std_logic;
        en       : in std_logic;
        data_in  : in std_logic_vector(N - 1 downto 0);
        data_out : out std_logic_vector(N - 1 downto 0)
    );
end g_register;

architecture Behavioral of g_register is
begin
    process (rst, clk) is
    begin
        if rst = '1' then
            data_out <= (others => '0');
        elsif rising_edge(clk) then
            if en = '1' then
                data_out <= data_in;
            end if;
        end if;
    end process;
end Behavioral;

My testbench code (g_register_testcases.vhd):

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity g_register_testcases is
end g_register_testcases;

architecture Behavioral of g_register_testcases is
    signal clock    : std_logic                    := '0';
    signal reset    : std_logic                    := '0';
    signal enable   : std_logic                    := '0';
    signal data_in  : std_logic_vector(7 downto 0) := "00000000";
    signal data_out : std_logic_vector(7 downto 0) := "00000000";

    component g_register is
        generic (
            N : integer := 8
        );
        port (
            rst      : in std_logic;
            clk      : in std_logic;
            en       : in std_logic;
            data_in  : in std_logic_vector(N - 1 downto 0);
            data_out : out std_logic_vector(N - 1 downto 0)
        );
    end component;
begin
    clock <= not clock after 10 ns;

    UUT : g_register
    generic map(8)
    port map(
        rst      => reset,
        clk      => clock,
        en       => enable,
        data_in  => data_in,
        data_out => data_out
    );

    process is
    begin
        reset <= '1';

        wait for 20 ns;

        reset   <= '0';
        enable  <= '1';
        data_in <= "11111111";

        wait for 20 ns;
    end process;

end Behavioral;

Simulation results

Behavioral Simulation

Post-synthesis Functional Simulation

It is my understanding that the above code should be correctly synthesized as flip-flops, but the output value doesn't change in the post-synthesis simulation even when enable is high (which is always the case here). What did I do wrong?

As an aside, I have this warning message of which I don't know what to make. Relevant?

[VRFC 10-4940] 'g_register' remains a black box since it has no binding entity ["~/project/project.srcs/sim_1/new/g_register_testcases.vhd":29]

I'm using Vivado 2024.2.

本文标签： vhdlVivado Differing behavior between Behavioral and PostSynthesis Functional SimulationStack Overflow