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In the MESI_Three_Level protocol of GEM5 simulator, there are L0, L1, L2, dir and dma state machines. L0 and L1 cache controllers simulate private caches for processor cores, which are implemented within the cores of real chips. The L2 cache controller, which includes cache memory and directory memory, simulates LLC and is typically implemented in the LLC part of a chip slice.

  1. But where is dir controller implemented in a real chip?
  2. Where is its directory memory stored?

The questions arise when i read MESI_Three_Level code and are not specific to GEM5 simulator. I want to know where is directory memory stored generally in real chips. I am not unsure whether my understanding is correct, please correct me if there are any misunderstandings. Thanks!

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